Project Topic: RISC-V

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Project Topic: RISC-V

RISC-V is an Instruction Set Architecture(ISA) based microprocessor designed under the principles of Reduced Instruction Set Computer(RISC). RISC-V is based on register-register operations and simple set instructions. RISC-V implementations can be from both open and close sources with various options to choose from. RISC-V can be operated in various languages such as Verilog, VHDL, Chisel, etc., and can be used in different platforms. RISC-V is a multiprocessor core that requires a system to operate. RISC-V foundation maintains the standard of RISC-V and includes foundation members like Codasip, Parallel Ultra Low Power(PULP), etc. The PULP, one of the founding members of the RISC-V has developed various types of RISC-V cores such as RI5CY, Micro riscy, Zero riscy, and Ariane. These versions of RISC-V cores can be used for open-source platforms provided by the PULP. The motive of this foundation is to develop a rich ecosystem of hardware and software which could dominate the companies like ARM and Intel. There is also some downside on RISC-V. Since it’s an open-source, it’s hard to manage a single standard of RISC-V. Likewise, the implementation of RISC-V in real-life applications and its verification is quite complex. In my research, I will focus on the various types of RISC-V multiprocessors, platforms of RISC-V, where it stands compared to other processors, and its drawbacks

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